As conventional lithography (193i) has reached its limit due to continuously shrinking feature size, alternative approaches have emerged. Among the alternative approaches, directed self-assembly (DSA) has been proven as a promising candidate to generate periodic patterns in a large area, such as contact holes or vias holes in a contact layer of an integrated circuit (IC). These patterns are usually small, presenting challenges to conventional fabrication processes. In a typical DSA process, a guide pattern (also called a template) is formed over a wafer by a lithography process, and then a block copolymer is deposited into the guide pattern and annealed to form polymeric cylinders. The polymeric cylinders are then used for further processing the wafer, for example, to form contact holes.
However, existing manufacturing flows based on DSA are not completely satisfactory. For example, the shape and size of guide patterns are usually not optimized for the DSA process. For another example, even though sub-resolution assistant features (SRAF) have been used in the past to improve photolithography performance, the use and design of such SRAF have not been optimized for the DSA process. Improvements in these areas are desired.